IMPLEMENTATION OF AREA OPTIMIZED REVERSIBLE LOGIC BASED ADAPTIVE RECURSIVE KARATSUBA
Nowadays, efficient binary multiplication is required by computationally intensive applications like DSP, image processing, floating point processors, and communication technologies. This block often consumes the most power and time. In order to cut down on time, this study suggests an effective architecture for unsigned binary multiplication. A 1616-bit multiplier based on the Vedic Karatsuba algorithm has been created. It is optimized utilizing a square-root carry-select-adder, reversible logic, and an adaptive and recursive technique. Verilog was used to code the designs, while Xilinx was used to synthesis them.