VALIDATION OF CMOS REVERSIBLE LOGIC GATES AT 16nm REGIME
In ancient times the VLSI technology has demand but in nowadays it has been increased rapidly because of low power consumption, less area is occupied and high speed. In VLSI,CMOS technology was highly preferred because CMOS generates both logic 0 and 1 whereas NMOS generates only logic 1 i.e; VDD and PMOS generates only logic 0 i.e; VSS. By using the VLSI technology the size of the circuits are reducing, the cost of the device reduces, and it has higher reliability. In this paper we use CMOS Reversible gates to maximise the speed, reducing energy consumption and reduces the power dissipation whereas reversible gates consists of Feynman Gate, Peres Gate, Modified Fredkin Gate, Modified Toffoli Gate and Reversible Full Adder using TSG.