Design and Analysis of Three-Stage Comparator and Its Modified Version with Fast Speed and Low Kickback

Authors

  • B. Abhigna
  • S. Sreeja
  • K. Renuka
  • T. Pullaiah

Abstract

This paper proposed a CMOS Three modelled comparator and its new version to enhance the speed and reduce the noise. When validate with conventional comparators this proposed comparator will enhance additional amplification structure, with this the efficiency of the proposed model will increase enormously. With this the proposed model the speed of the comparator will increases because inputs are driven with input pairs for regeneration and amplified stage. With this structure speed increased a lot. By this proposed model noise generated by the Pmos topology will dwindles by the use of Nmos pair. In proposed model an extra signal has been configured in the regeneration stage, in turn will enhance the speed of the proposed circuit will increase further. To validate the proposed model, using 16nm BSIM4 Model. By comparison, proposed model dictates that three stage circuits enhance speed by 34% and dwindles noise by several times. The proposed model has been validated through Mentor graphics 16nm BSIM4 Technology.

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Published

2022-07-07