Design and Simulation of Multistage Hybrid full adder using CMOS 16nm Technology


  • S. Sukeerthi
  • N. Sirisha
  • P. Varshitha
  • S. Sindhu
  • J. Sunil Kumar


The assessment of the timing behavior of the arithmetic circuits is one of the most challenging aspects of the design of extremely large scale integrated circuits. The concept of logical effort provides a helpful framework for analyzing and assessing the timing behavior of typical CMOS (C-CMOS) built circuits. This approach does not work well for hybrid circuits. However, various hybrid circuits that are faster than C-CMOS ones and utilize less power than C-CMOS ones have been proposed for usage in a wide range of devices, including portable and Internet of Things devices. In this respect, it is unavoidable that a straightforward and effective timing behavior approach, such as traditional logical effort, be present and used for the study of hybrid adder circuits. This paper presents an effective analysis and modeling approach to help designers evaluate the timing behavior of hybrid full adder circuits at the block level and anticipate their performance in multistage circuits. For precise selection and optimization of the hybrid adder cells that can be seen on a single test bench, the gain and selection factor is recommended in order to optimize the trade-off between energy efficiency and performance. Utilizing 16-nm CMOS technology, the suggested technique is examined.