Full Adder Using High performance 10T-XOR-XNOR Cell

Authors

  • K. Divya Sri Sai Durga
  • S. Sravya
  • M. Sathwika
  • M. Radhika

Abstract

The design of an arithmetic circuitry mainly makes use of the new blended model. The strength of the circuit, holding duration, potential charge utility, and the efficiency of a complete adder all heavily influence how well the circuit operates. This project results in the construction of a ten-transistor logic circuit with high speed and low power consumption that simultaneously creates effective fluctuations and an output delay. Tanner software simulation employing 45nm technology is used to determine the performance efficiency of the planned circuit. The created circuit reduces the PDP factor over the pre-existing XOR-XNOR versions by at least 15%. Using the XOR-XNOR circuitry that has previously been created, as well as existing sum and carry generating blocks, we are presenting two distinct designs of complete adders in this project. In terms of power fluctuation product, the planned full adders provide improvements of between 10% and 40% over previous versions. The suggested full adders are installed in multistage full adder circuits to calculate the driving capabilities. The findings demonstrate that, among all the full adders, two of the developed full adders provide the best performance for a higher number of data bits. Keywords: PDP factor

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Published

2022-07-04