Design and Implementation of High-Speed Hybrid Full Adder by Using 16nm

Authors

  • Adepu Shivani
  • Digajarla Snehitha
  • Malamanti Mounika
  • T. Pullaiah

Abstract

Using transmission gates pass transistors, and conventional CMOS logic, a hybrid complete adder is created. The toolset for Mentor Graphics has been used to analyse the circuit's performance. Twenty-two (22) current Full Adder circuits have been examined with the performance parameters for comparative analysis a word length of 64 bits has also been put in place to test how well the proposed FA can grow. Only the proposed FA and five other designs can work without a buffer between phases when 64 bits are added. The entire adder being suggested, which uses only 17 transistors, the suggested design, which accounts for low power delay product, performs admirably in terms of power consumption and delay, according to simulation findings. The suggested hybrid FA circuit provides a compelling option in the data route design of contemporary high-speed Central Processing Units, according to the simulation findings. The proposed one bit full adder has been validated using Mentor 16nm Technology.

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Published

2022-07-04