Exploring New XOR and XNOR Gates to Create a Low-Power and Quick Full Adder
New circuits are suggested in this study for simultaneous XOR-XNOR and XOR/XNOR operations. There are considerable degrees of power use optimization in the proposed Circuits Short circuit output power loss is minimized, and output capacitance is kept to a minimum. We also offer six novel hybrid circuits for a 1-bit full-adder based on the unique full-swing gates that employ XOR-XNOR or XOR/XNOR (FA) (FA). Each suggested circuit offers benefits in terms of speed, power utilisation, power delay product (PDP), ability to drive, and other characteristics. To evaluate how well the suggested designs operate, a number of HSPICE and Cadence Virtuoso simulations are done. Based on the technology model for the 65-nm CMOS process, simulations demonstrate that the recommended designs are quicker and consume less power than alternative FA systems. Using a unique approach to transistor size, the PDP of the circuits is improved. The recommended technique rapidly determines the optimal value for the optimum PDP by using the numerical computing particle swarm optimization methodology. The modifications of the output capacitance, supply and threshold voltages, input noise immunity, and transistor size of the suggested circuit are all investigated.