Design of an Approximate Multiplier with Novel Dual-Stage 5: 2 Compressors

Abstract

High-speed multimedia applications have ushered in a new era of approximation-based error-tolerant circuits. These programmes provide great performance at the expense of precision. In addition, such approaches minimize system complexity, latency, and power consumption. When compared to existing systems, this research examines and gives recommendations for the design and analysis of two approximation compressors that are smaller, quicker, and consume less power while maintaining the same accuracy. The suggested designs have been thoroughly examined and projected on several sizes, including time and area. The proposed estimate 5: 2 com-pressor decreased area and latency when compared to the approximate multiplier using a 4: 2 com-pressor.16 Bit Dadda multipliers are used with the given compressors. In terms of how accurate they are, these multipliers are the same as the best approximation multipliers on the market today. The research is being expanded to look at how the Suggested architecture can be used in error-tolerant applications like image smoothening.